Multi-Stage Organic Logic Circuits Using Via-Hole-Less Metal Interconnects

  • Park, H.
  • Yoo, H.
  • Lee, C.
  • Kim, J.-J.
  • Im, S.G.
Citations

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Citations

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초록

Multi-metal interconnection is a crucial technology for the development of large-scale integrated circuits (ICs). However, organic semiconductors are not robust enough to be compatible with conventional lithography-and-etching-based via-forming methods. Thus, an alternative metal interconnect method is required for successful organic IC implementation. In-situ patterning of a dielectric polymer through a shadow mask while depositing in vapor phase possibly addresses the issues in both solvent susceptibility and process complexity. Here we report multi-stage organic logic circuits with a multi-level metal interconnection scheme based on patterned interlayer dielectrics via vapor phase deposition. We implement an exclusive OR circuit composed of four 2-input NAND gates and three-level metal interconnections to demonstrate the potential of the proposed solvent-free metal interconnection scheme. © 1980-2012 IEEE.

키워드

interconnectionOrganic semiconductorsthin-film circuitsthin-film transistorsvapor depositionDielectric materialsEtchingIndium compoundsIntegrated circuit interconnectsLogic circuitsMetalsTiming circuitsConventional lithographyCrucial technologyDielectric polymersInter-layer dielectricsLarge scale integrated circuitMetal interconnectionsMetal interconnectsVapor phase depositionComputer circuits
제목
Multi-Stage Organic Logic Circuits Using Via-Hole-Less Metal Interconnects
저자
Park, H.Yoo, H.Lee, C.Kim, J.-J.Im, S.G.
DOI
10.1109/LED.2020.3027423
발행일
2020-11
유형
Article
저널명
IEEE Electron Device Letters
41
11
페이지
1685 ~ 1687