A 13.2-kSPS Data Rate, 5.1-G$\Omega$ Input Impedance Read-Out IC for DC Measurements

초록

A high input impedance read-out integrated circuit (IC) for DC measurements has been implemented. The proposed read-out IC consists of a capacitively coupled instrumentation amplifier (CCIA) and an incremental delta-sigma ( DE) analog- to-digital converter (ADC). An impedance boosting technique, combining the conventional positive-feedback loop with a proposed fine current compensation loop (FCCL), is introduced to enhance the input impedance of the CCIA. Additionally, the proposed structure chops the entire signal chain at a global chopping frequency of 13.2 kHz, which is higher than the 1/ f corner frequency of the CCIA's main amplifier. This approach further increases the input impedance of the CCIA and eliminates the need for RRL and an analog low pass filter (LPF), thereby reducing circuit complexity and area. Local auto-zeroing and correlated double sampling techniques are also used to suppress the offset and 1/ f noise of the read-out IC. The 18-bit ADC operates at a sampling clock of 4 MHz with a third-order cascade of integrators (CoI) digital filter. Implemented in a 0.13 mu m CMOS process, the prototype chip occupies an area of 3.808 mm(2) and draws 1.32 mA from a 5 V supply. The input impedance is boosted from 4.4 MS1 to 5.1 G S1, corresponding to an impedance boosting factor of 1153. The measurement results show an input- referred noise of 2.4 mu V (RMS) with a conversion time of 0.076 ms. The input range of the ROIC is 4.8 V and it achieves the Schreier figure of merit of 164.9 dB.

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