Impact of annealing temperature on the performance and stability of a-gallium-zinc-tin-oxide thin-film transistors

초록

This study presents a comprehensive investigation into the performance and bias-stress stability of amorphous gallium-zin-tin oxide (a-GZTO) thin-film transistors (TFTs) modulated by post-deposition thermal annealing. Furthermore, the correlation between physical defect states and electrical characteristics reveals the fundamental origins of device enhancement. As the annealing temperature increases from 300 degrees C to 500 degrees C, the Urbach energy (Eu) decreases from 226.95 meV to 224.07 meV, indicating a reduction in localized trap states within the amorphous network. This defect suppression directly correlates with significant improvements in device characteristics. Specifically, the field-effect mobility increases from 17.1 to 27.0cm2 Vs-1, while the threshold voltage shift under positive bias stress (PBS) substantially decreases from 2.74 V to 0.70 V. Through transmission line method analysis, the contact resistance (Rc) and sheet resistance (Rsh) are extracted, verifying that increasing the annealing temperature simultaneously reduces the Rsh (4.01 & times; 103 Omega sq-1 to 4.66 & times; 102 Omega sq-1) and Rc (3.29 & times; 105 Omega to 1.85 & times; 104 Omega). A comprehensive analysis of optical absorption tails, activation energy and PBS instability systematically demonstrates that thermal annealing is a highly effective strategy to mitigate sub-gap defect states, achieving both the high electrical performance and operational reliability of a-GZTO TFTs.

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