Compositional engineering of Si-doped ZnSnO thin-film transistors for high-performance integrated logic circuits

초록

Amorphous oxide semiconductor thin-film transistors (TFTs) have emerged as promising candidates for next-generation electronics due to their high carrier mobility (> 10 cm(2)/V & centerdot;s) and compatibility with low-temperature, large-area processing. However, simultaneously achieving high performance and long-term stability remains challenging. In this study, we systematically investigate amorphous Si-Zn-Sn-O (a-SZTO) TFTs, with controlled Si composition engineering enabling a field-effect mobility (& micro;(FE)) of up to 28 cm(2)/V & centerdot;s and a reduced subthreshold swing (S.S.) of 0.295 V/dec, while maintaining on/off current ratios above 10(8). Transmission line method (TLM) analysis revealed a systematic increase in contact and sheet resistance with increasing Si content, which is correlated with carrier concentration modulation. X-ray photoelectron spectroscopy (XPS) confirmed enhanced metal-oxygen bonding and suppressed oxygen vacancy components, indicating effective defect reduction. Consequently, improved bias stability was achieved under both negative and positive bias stress (10,800 s), with highly Si-doped devices exhibiting a threshold voltage shift (Delta V-TH) below 1 V. Furthermore, NOT, NAND, and NOR logic circuits were successfully implemented using only n-type oxide TFTs. The NOT gate demonstrated a maximum voltage gain of 33.45. These results demonstrate that Si composition engineering enables simultaneous control of electrical performance and reliability, providing a strategy for high-performance and stable oxide semiconductor logic circuits.

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