A Single-Ended MTA PAM-4 Receiver With Analog-Front-End Nonlinearity Compensation Using MTA-Error Correction Scheme for Memory Interfaces

초록

This paper presents a single-ended four-level pulse amplitude modulation (PAM-4) receiver for maximum transition avoidance (MTA)-coded signaling, incorporating an analog-front-end (AFE) non-linearity compensation technique using a novel MTA-error correction scheme (MTA-ECS). By exploiting the restricted-transition property of MTA coding, the proposed MTA-ECS suppresses nonlinearity-induced inter-symbol interference (ISI) and restores eye symmetry while reducing receiver power consumption through sampler clock-gating. Additionally, an asymmetric transition-based decision feedback equalizer (DFE) is introduced to correct residual eye-dependent ISI with reduced routing complexity and hardware cost compared with conventional PAM-4 DFEs. Fabricated in a 28-nm CMOS process, the prototype receiver achieves 22 Gb/s/pin operation with an energy efficiency of 0.61 pJ/bit and a linearity compensation efficiency of 0.044 pJ/bit. The proposed receiver extends the worst-case PAM-4 timing margin from 0.05 UI to 0.325 UI at a bit error rate of 10(-12), demonstrating its effectiveness for low-power, high-speed memory interfaces.

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