Flash synaptic arrays with improved endurance-retention trade-off and backpropagation capability for efficient on-chip training

초록

Neuromorphic systems that utilize the computation capability of nonvolatile memory devices are arising as a next-generation energy-efficient hardware platform for artificial intelligence. Especially, an on-chip trainable neuromorphic system is in demand for various edge applications. For on-chip training, the selective synaptic weight update operation with low-power and high-endurance is required in an array structure capable of backpropagation, while also maintaining CMOS compatibility. In this work, a novel charge-trap synaptic device that fulfills all these requirements is developed for the first time by optimizing the charge injection path structure and utilizing lateral charge migration in the Si3N4 charge trap layer. The thin-film transistor-based NOR-type synaptic array achieves low-power selective program/erase and accurate bidirectional current sum operation. Also, the synaptic array is monolithically integrated with CMOS peripheral circuits. Combined with pulse-width modulation neuron operation, the proposed WSP synaptic array and circuits experimentally demonstrate the key hardware building blocks required for backpropagation-compatible on-chip training. Through hardware-aware simulations incorporating experimentally measured device, array, and circuit characteristics, the on-chip fewshot learning capability of the proposed hardware platform is evaluated using optimized hardware-friendly algorithms.

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